# Simple method analysis of PLL design and provide effective debugging methods

Designing and debugging phase-locked loop (PLL) circuits can be complex unless engineers have a solid understanding of PLL theory and the logic development process. This article describes an easy way to design a PLL and provides an efficient, logical way to debug PLL problems.

Designing and debugging phase-locked loop (PLL) circuits can be complex unless engineers have a solid understanding of PLL theory and the logic development process. This article describes an easy way to design a PLL and provides an efficient, logical way to debug PLL problems.

simulation

Estimating the specifications of a PLL circuit can be difficult without simulating under specific conditions. Therefore, the first step in PLL design should be simulation. We recommend that engineers use ADIsimPLL software to run simulations based on system requirements, including reference frequency, step frequency, phase noise (jitter), and frequency spurious limits.

Many engineers are at a loss as to how to choose a reference frequency, but the relationship between the reference frequency and the output frequency step is actually quite simple. With an integer-N PLL, the output frequency step is equal to the frequency at the input of the phase-frequency detector (PFD), which is equal to the reference frequency divided by the reference divider R. With a fractional-N PLL, the output frequency step is equal to the PFD input frequency divided by the MOD value, so you can use a higher reference frequency for smaller frequency steps. When deciding to use integer-N or fractional-N division, phase noise performance can be sacrificed for frequency stepping, ie, lower PFD frequencies have better output frequency resolution at the expense of phase noise performance.

For example, Table 1 shows that if a fixed frequency output and extremely large frequency steps are required, an integer-N PLL such as the ADF4106 should be preferred because it has better overall in-band phase noise. Conversely, if smaller frequency steps are required, a fractional-N PLL (such as the ADF4153) should be preferred because its overall noise performance is better than an integer-N PLL. Phase noise is a fundamental PLL specification, but data sheets cannot specify performance parameters for all possible applications. Therefore, it is critical to simulate first and then test with actual hardware.

Table 1. Phase Noise Determining PLL Selection

Even when simulating a PLL circuit with ADIsimPLL under real conditions, the results may not be sufficient unless a real reference as well as a model file for a voltage controlled oscillator (VCO) are included. If not included, the simulator will use the ideal reference and VCO for simulation. If high simulation accuracy is required, the time spent editing the VCO and reference library files will be worthwhile.

PLLs use a negative feedback control system similar to amplifiers, so the concepts of loop bandwidth and phase margin still apply here. Typically, the loop bandwidth should be set to less than one tenth of the PFD frequency, with a safe range of 45° to 60° phase margin. In addition, simulation and prototyping on a real board should be performed to confirm that the circuit meets the PCB layout specifications for parasitic components, resistor tolerances, and loop filter capacitance.

In some cases, suitable resistor and capacitor values ​​are not available, so engineers must determine if other values ​​can be used. There is a small function hidden in the Tools menu of ADIsimPLL called “BUILT”. This feature converts resistor and capacitor values ​​to the closest standard engineering values, allowing designers to return to the simulation interface to verify the new values ​​for phase margin and loop bandwidth.

register

ADI PLLs offer many user-configurable options and a flexible design environment, but also present the challenge of determining the value stored in each register. A convenient solution is to use the evaluation software to set the register values, even when the emulator is not connected to the PCB. The setup file can then be saved as a .stp file or downloaded to the evaluation board. Figure 1 shows the ADIsimPLL simulation results, providing suggested register values ​​for parameters such as VCO core current.

Figure 1. ADIsimPLL simulation software provides suggested values ​​for register settings

Schematic and PCB Layout

There are a few things to keep in mind when designing a complete PLL circuit. First, it is important to match the PLL’s reference input port impedance to minimize reflections. Also, keep the capacitor in parallel with the input port as small as possible because it reduces the slew rate of the input signal and increases the PLL loop noise. Refer to the input requirements on the PLL data sheet for more details.

Second, separate the analog power supply from the digital power supply to minimize interference between them. The VCO supply is particularly sensitive, so spurs and noise here can easily couple to the PLL output. For more considerations and details, refer to Sourcing a Fractional-N Voltage Controlled Oscillator (VCO) to Reduce Phase Noise Using a Low Noise LDO Regulator (CN-0147)

Again, the resistors and capacitors used to form the loop filter should be placed as close as possible to the PLL chip and use the values ​​suggested in the simulation file. If you find it difficult to lock onto the signal after changing the loop filter component values, try using the values ​​originally used on the evaluation board.

For PCB layout, the main principle is to separate the input from the output to ensure that the digital circuits do not interfere with the analog circuits. For example, if the SPI bus is too close to the reference input or the VCO output, the VCO output can cause spurs at the PLL output when accessing the PLL registers.

From a thermal design perspective, a thermally conductive ground pad can be placed under the PLL chip to ensure that heat flows through the pad to the PCB and heat sink. Designers should calculate all thermal parameters of the PLL chip and PCB for use in extreme environments.

Effective use of MUXOUT

At the beginning of the debug phase, if the PLL is not locked, it can be difficult to determine where to start. As a first step, you can use MUXOUT to see if all internal functional units are working properly, as shown in Figure 2. For example, MUXOUT can Display the R counter output, indicating that the reference input signal is good and the register content was successfully written. The MUXOUT also checks the lock status of the detector and the divide-by-N output in the feedback loop. In this way, the designer can determine whether each divider, gain or frequency value is correct. This is the basic procedure for debugging a PLL.

Figure 2. MUXOUT Pin Auxiliary PLL for Debugging

time domain analysis

When debugging the PLL, use time domain analysis to demonstrate that the data written to the registers on the Serial Peripheral Interface (SPI) bus is correct. Although read and write operations take a long time, please ensure that the SPI timing is within specifications and crosstalk between different lines is minimized.

Timing diagrams in the PLL data sheet should be consulted for data setup time, clock speed, pulse width, and other specifications. Make sure to leave enough slack to meet timing requirements under all conditions. Use an oscilloscope to check that the clock and data edges are in the correct position in the time domain. If the clock and data lines are too close, crosstalk can cause clock energy to couple through the PCB routing to the data lines. This coupling can cause glitches on the data lines on the rising edge of the clock. Therefore, it is necessary to check these two lines when reading and writing the register, especially if there is an error in the register. Make sure the line voltage meets the specifications in Table 2.

Table 2. Logic Inputs

Spectrum analysis

Problems in the frequency domain are more common and complex. If using a spectrum analyzer, you should first check that the PLL output is locked; if the waveform has stable frequency peaks, it is locked. If it is not locked, the steps described above should be followed.

If the PLL is locked, narrow the spectrum analyzer bandwidth to determine if the phase noise is within acceptable limits and verify the test results against the simulation results. Measure phase noise at certain bandwidths, such as 1 kHz, 10 kHz, and 1 MHz.

If the results are not as expected, the loop filter design should be reviewed first to check the true values ​​of the components on the PCB. Then, check whether the phase noise of the reference input agrees with the simulation results. The PLL simulated phase noise should be close to the real value unless external conditions are different, or wrong values ​​are written to the registers.

Power supply noise is not negligible, even when low noise LDOs are used; both the DC-DC converter and the LDO can be sources of noise. Noise spectral densities shown in LDO data sheets often affect noise-sensitive devices such as PLLs (see Figure 3). Choose a low-noise power supply for the PLL, especially if you need to supply the core current for the VCO.

Figure 3. LDO Noise Spectral Density

There are typically four types of spurs at the output of a PLL: PFD or reference spurs, fractional spurs, integer boundary spurs, and spurs from external sources such as power supplies. All PLLs have at least one type of spur, and while these can never be eliminated, in some cases, trade-offs between different types of spurs or frequencies can improve overall performance.

To avoid reference spurs, check for the rising edge of the reference signal. If the edge is too fast or the edge amplitude is too large, it will cause serious harmonic phenomenon in the frequency domain. Also, carefully check the PCB layout to avoid crosstalk between input and output.

To minimize fractional spurs, the perturbation can be added to force the fractional spurs into the noise floor, but doing so will increase the noise floor slightly.

Integer boundary spurs are uncommon and only occur when the output frequency is too close to an integer multiple of the reference frequency for the loop filter to filter out. An easy solution to this problem is to rescale the reference frequency scheme. For example, if a boundary spur occurs at 1100 MHz, and the output is 1100.1 MHz and the reference input is 20 MHz, the spur can be removed by changing the reference frequency to 30 MHz using a 100 kHz loop filter.

in conclusion

Debugging a PLL requires a solid understanding of the PLL, and many problems can be avoided if extra care is taken during the design phase. If the problem occurs during the debugging phase, please follow the suggestions described in this article to analyze the problem one by one and solve the problem step by step.